I. Field of the Disclosure
The technology of the disclosure relates to providing capacitors in semiconductor dies for use by integrated circuits.
II. Background
Mobile communication devices have become common in current society. The prevalence of these mobile devices is driven in part by the many functions that are now enabled on such devices. Demand for such functions increases processing capability requirements and generates a need for more powerful batteries. Within the limited space of the housing of the mobile communication device, batteries compete with the processing circuitry. These and other factors contribute to a continued miniaturization of components within the circuitry.
Miniaturization of the components impacts all aspects of the processing circuitry including the transistors and other reactive elements in the processing circuitry, such as capacitors. One miniaturization technique involves moving some reactive elements from the printed circuit board into the integrated circuitry. One technique for moving reactive elements into the integrated circuitry involves creating metal-on-metal (MoM) capacitors during back end of line (BEOL) integrated circuit fabrication. Each integrated circuit complies with a collection of process parameters that allow circuits to be manufactured and to operate under desired specifications (sometimes called a “process window”). The process window may be unique to a particular integrated circuit or may be duplicated across a product line or have other application as desired, but the existence of a corresponding process window effectively sets forth the thresholds with which an integrated circuit must comply to be suitable for use as designed (e.g. an integrated circuit in a mobile communication device).
Many current BEOL MoM capacitors use a two element interdigitated structure. Such capacitors are created using masks and metal deposition processes. In such processes, a substrate may be provided and a mask is positioned thereon. A metal deposition technique is used to generate the two conductive elements of the capacitor. In this regard, the two conductive elements form the positive and negative nodes of the capacitor. Since capacitance is a function of the size of the conductive elements, increased capacitance is achieved through larger positive and negative nodes. However, such larger nodes increase the footprint of the capacitor, defeating the miniaturization goals, and such larger nodes conflict with the process window and increase local stress significantly.
One approach used to create higher capacitance MoM devices is providing a layered interdigitated structure whereby additional layers of interdigitated structures are stacked vertically on top of each other. In this manner, the size of the nodes is effectively increased because each node has conductive elements in multiple planes. These larger nodes create a capacitor having a higher capacitance because each of the layers contributes to the overall capacitance of the device. Furthermore, additional capacitance is created between the layers. In some MoM devices, alternating layers of the interdigitated structures are rotated relative to layers above and below one another.
However, this layered approach (whether with rotation or not) suffers from cumulative errors resulting from misalignments of the conductive elements during the manufacturing process. That is, a surface irregularity on a first layer will become exacerbated as additional layers are stacked on top of the irregularity. At a minimum, each inter-metal dielectric (IMD) surface will cause the next film surface to have the same irregularity and such irregularity will negatively affect the process window. Further, it is possible that each additional layer will exaggerate the irregularity. As technologies continue to scale smaller, the relative distortion of such surface irregularity may become larger and have greater impact on the process window than in prior technologies since the BEOL process window has tighter tolerances as size becomes smaller (e.g., a one nanometer irregularity may not matter on a one micrometer scale device, but becomes much more significant on a twenty nanometer scale device (where such irregularity may account for a five percent variation)).